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Not rated yet.I/O subsystem with header and error detection code generation and checking
United States Patent 5463762
Apparatus is provided for use in an Input/Output (I/O) subsystem. The I/O subsystem is coupled to a serial data transfer medium that transmits data from a sender to a recipient. The I/O subsystem processes a frame comprising user defined data and frame control data. The frame is received over the serial data transfer medium. The apparatus includes a mechanism for receiving and validating the frame from the serial data transfer medium. The receiving mechanism transmits the user defined data to a first-in, first-out (FIFO) buffer. A mechanism is provided for forming a block header. The block header comprises control data that are used by the recipient of the user defined data. The block header forming mechanism is distinct from the FIFO buffer. A switching mechanism is coupled to receive the block header and a subset of the user defined data. The recipient has a parallel storage medium. The switching mechanism transmits either the block header or the subset of the user defined data to the parallel storage medium. A control mechanism provides signals to configure the switching mechanism to alternately transmit the block header and the subset of the user defined data to the parallel storage medium. By alternating the block header and data, a data block is formed having a size that equals the native sector size of the recipient.
Inventors:
Morrissey, Douglas E. (Exton, PA)
Cavanagh Jr., Edward T. (Norristown, PA)
Ng, Kin H. (Glenmoore, PA)
Application Number:
Publication Date:
10/31/1995
Filing Date:
12/30/1993
Export Citation:
Unisys Corporation (Blue Bell, PA)
Primary Class:
Other Classes:
714/E11.032
International Classes:
G06F11/10; G06F13/38; (IPC1-7): G06F1/00
Field of Search:
395/575, 395/275, 395/250, 364/238.2, 364/238.3, 364/239.6, 364/239.7, 364/240.8, 364/242.2, 371/37.1, 371/37.7, 371/2.1, 371/48, 371/49.1, 370/60, 370/85.15
View Patent Images:
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US Patent References:
5371897Brown et al.395/2755329625Kannan et al.395/2755243699Nickolls et al.395/2755243596Port et al.5235595O'Dowd5185862Casper et al.395/2505133078Minassian et al.5107489Brown et al.370/58.25007051Dolkas et al.370/85.14899333Roediger370/604875206Nichols et al.370/85.154872160Hemmady et al.370/604866609Calta et al.4805090Coogan364/2004777595Strecker et al.4768190Giancarlo4514823Mendelson et al.4486739Franaszek et al.
Foreign References:
EP0402295Method and system for transmitting signals over a fibre optic link.EP0412268Apparatus for interconnecting a control unit having a parallel bus with a channel having a serial link.
Other References:
IBM, "ESA/390.TM. Channel Connectivity", brochure.
IBM Corporation, "Enterprise Systems Architecture/390, ESCO I/O Interface", SA22-7202-01, Sep. 1991.
"Am79168/Am79169TAXIchip.TM." Transmitter/ Receiver PRELIMINARY, Feb. 1991.
Primary Examiner:
Beausoliel Jr., Robert W.
Assistant Examiner:
Decady, Albert
Attorney, Agent or Firm:
Ratner & Prestia
What is claimed:
1. In an Input/Output (I/O) subsystem coupled to a serial data transfer medium that transmits data from a sender to a recipient, the I/O subsystem processing a frame comprising user defined data and frame control data received over the serial data transfer medium, apparatus comprising:
a processor for determining a block header size and a native sector s
means coupled to the processor for receiving and storing the block header size and th
means for receiving and validating the frame from the serial data transfer medium, and for transmitting the user defined data to a first-in, first-out (FIFO)
means for forming a block header having said block header size, the block header comprising control data that are used by the recipient, the block header forming means being independent from the FIFO
switching means connected to the block header forming means to receive the block header therefrom and to the FIFO buffer to receive a subset of the user defined data therefrom, for transmitting one of the block header and the subset of the user defined data to a parallel storage med and
control means separate and distinct from the processor and operating without interfering with operation of the processor and independently therefrom, for providing signals that configure the switching means to alternately transmit: (1) the block header from the block header forming means until a number of bytes equal to the block header size have been transmitted and (2) the subset of the user defined data from the FIFO until a number of bytes equal to the native sector size have been transmitted, the native sector size being differerent from a size of the frame,wherein said control means provide said signals to the switching means based on how many bytes of data have been transmitted to the parallel storage medium.
2. Apparatus according to claim 1, wherein the I/O subsystem is the I/O subsystem of a mass storage device controller, and the recipient is a mass storage device, the I/O subsystem coupling the device controller to a host processor system via the serial data transfer medium, the device controller receiving the frame from the host processor and transmitting the user defined data to the mass storage device within the data block.
3. Apparatus according to claim 2, wherein the frame includes an amount of user defined data that is greater than the native sector size of the mass storage device and the control means includes means for dividing the user defined data in the frame into a plurality of data blocks.
4. Apparatus according to claim 3, wherein the block header forming means comprises a counter for providing consecutively numbered block identification numbers for inclusion in the block header of each successive frame, each having an amount of data less than the native sector size.
5. Apparatus according to claim 3, wherein the block header forming means further comprises means for generating a constant sequence of characters for inclusion in each block header.
6. Apparatus according to claim 1, wherein the I/O channel is the I/O subsystem of a host processor system, and the recipient is the host processor, the I/O subsystem coupling the host processor system to a mass storage device controller via the serial data transfer medium.
7. Apparatus according to claim 6, wherein the user defined data include a plurality of pad data that are not used by the recipient, and the control means includes:
means for disabling the block header forming means, and
means for stripping a plurality of pad data from the user defined data before transmission to the parallel storage medium, including means for providing signals to configure the switching means to disable transmission of a predetermined number of characters in the user defined data.
8. In an Input/Output (I/O) subsystem coupled to a serial data transfer medium that transmits data from a sender to a recipient, the I/O subsystem processing a frame comprising user defined data and frame control data received over the serial data transfer medium, apparatus comprising:
a processor for determining a native sector s
means coupled to the processor for receiving and storing th
a first-in, first-out (FIFO)
means for receiving and validating the frame from the serial data transfer medium, and for transmitting the user defined data to the FIFO
means for forming an Error Detection Code (EDC) that has an EDC size and is used to detect errors in the user defined data, the EDC forming means being independent from
switching means connected to: (1) the FIFO buffer for receiving a subset of the user defined data having a subset size that is equal to a difference between the native sector size and the EDC size, and (2) to the EDC forming means for receiving the EDC, the switching means coupled to a data buffer for transmitting one of the subset of the user defined data and the EDC and
control means separate and distinct from the processor and operating without interfering with operation of the processor and independently therefrom, for providing signals that configure the switching means to successively transmit: (1) the subset of the user defined data until a number of bytes equal to the subset size have been transmitted to the data buffer and (2) the EDC, until a number of bytes equal to the native sector size have been transmitted to the data buffer, said native sector size being different from a size of the frame,wherein said control means provide said signals to the switching means based on how many bytes of data have been transmitted to the data buffer.
9. Apparatus according to claim 8, wherein the I/O channel is the I/O subsystem of a mass storage device controller, coupling the device controller to a host processor system via the serial data transfer medium, the device controller receiving the frame from the host processor and transmitting the user defined data in the data block to a mass storage device.
10. Apparatus according to claim 9, wherein the EDC forming means includes means for generating a parity bit for each respective byte of user defined data.
11. Apparatus according to claim 8, further comprising means for forming a block header having a block header size, the block header comprising control data that are used by the recipient, the block header forming means being distinct from the FIFO buffer, wherein:
the switching means is coupled to the block header forming means for receiving the block header data, and
the control means provides further signals that configure the switching means to transmit the block header data until a number of bytes equal to the block header size are transmitted to the data buffer, before the subset of the user defined data is transmitted to the data buffer.
12. Apparatus according to claim 11, wherein:
(1) the mass storage device has a native sector size, the frame includes an amount of user defined data that is greater than the native sector size of the mass storage device, and the control means includes means for dividing the user defined data in the frame into a plurality of data blocks, each having an amount of data less than th
(2) the block header forming means comprises:
(a) a counter for providing consecutively numbered block identification numbers for inclusion in the block header of each successive frame, each having an amount of data less than the native sector size, and
(b) means for generating a constant sequence of characters for inclusion in each block header.
13. Apparatus according to claim 11, wherein the control means includes means for configuring the switching means to alternately transmit the block header and the user defined data to the data buffer, including means for disabling transmission of the EDC.
14. In an Input/Output (I/O) subsystem having a parallel storage medium that stores a data block having a block header and a plurality of user defined data, apparatus for transferring the user defined data from the parallel storage medium to a serial link driver that transmits a frame of user defined data from a sender to a recipient over a serial data transfer medium, comprising:
a processor for determining a device information block (DIB)
means coupled to the processor for receiving and storing the DIB
means for receiving the data block from the parallel storage medium, removing the block header therefrom, and storing the user defined data in a first-in, first-out (FIFO)
means coupled to the parallel storage medium for comparing a value in the block header to a predetermined value to determine whether the data block received by the FIFO buffer is a desired data block, and for disabling transmission of the frame if the data block is not th
control data means for forming and transmitting control data from the sender of the frame to the recipient of the frame via a path that does not include the FIFO buffer, the control data having a control data size, the control data means being independent from the FIFO buffer and the processor and operating without interfering with operat
switching means coupled to the FIFO buffer for receiving the user defined data and to the control data means for receiving the control data, the switching means being coupled to the serial link driver for providing one of the user defined data and the control data to th and
data path control means separate and distinct from the processor and operating without interfering with operation of the processor and independently therefrom, for providing signals to configure the switching means to alternately transmit: (1) a number of bytes of the control data equal to the control data size and (2) a number of bytes of the user defined data equal to the DIB size to the serial link driver, thereby forming the frame, said data path control means providing said signals to the switching means based on how many bytes of data have been transmitted to the serial link driver.
15. Apparatus according to claim 14, wherein the I/O subsystem is the I/O subsystem of a mass storage device controller, coupling the device controller to a host processor system via the serial data transfer medium, the device controller receiving the data block from a mass storage device and transmitting the user defined data from the data block to the host processor in the frame.
16. Apparatus according to claim 15, wherein the comparing means includes:
means for examining a counter value within each data block received by the FIFO buffer, and
means for flagging an error condition if successive blocks that have non-consecutive counter values are received.
17. Apparatus according to claim 14, wherein the I/O subsystem is the I/O subsystem of a host processor system, coupling the host processor system to a mass storage device controller, to transmit frames to the device controller via the serial data transfer medium.
18. Apparatus according to claim 14, further comprising:
means for disabling and
means coupled to the switching means for generating a sequence of pad data characters,
wherein the data path control means transmits signals to configure the switching means to transmit the sequence of pad characters after the user defined data are transmitted.
19. In an Input/Output (I/O) subsystem having a parallel storage medium that stores a data block having a block header, a plurality of user defined data and an error detection code (EDC), apparatus for transferring the user defined data from the parallel storage medium to a serial link driver that transmits a frame of user defined data from a sender to a recipient over a serial data transfer medium, comprising:
a processor for determining a device information block (DIB)
means coupled to the processor for receiving and storing the DIB
a first-in, first-out (FIFO) buffer which receives and stores the user defined data from the par
means coupled to the parallel storage medium for comparing a value in the block header to a predetermined value to determine whether the data block in the parallel storage medium is
means for examining the user defined data in the FIFO buffer and the EDC to determine if any parity errors are present in t and
control data means for forming and transmitting control data from the sender of the frame to the recipient of the frame via a path that does not include the FIFO buffer, the control data having a control data size, the control data means being independent from the FIFO buffer and the processor and operating without interfering with operat
switching means coupled to the FIFO buffer for receiving the user defined data and to the control data means for receiving the control data, the switching means coupled to the serial link driver for providing one of the user defined data and the control data to th and
data path control means separate and distinct from the processor operating without interfering with operation of the processor and independently therefrom, for providing signals to configure the switching means to alternately transmit: (1) a number of bytes of the control data equal to the control data size and (2) a number of bytes of the user defined data equal to the DIB size to the serial link driver, thereby forming the frame, said data path control means providing said signals to the switching means based on how many bytes of data have been transmitted to the serial link driver.
20. Apparatus according to claim 19, wherein the I/O subsystem is the I/O subsystem of a mass storage device controller, coupling the device controller to a host processor system via the serial data transfer medium, and the recipient of the frame is a host processor system, the device controller receiving the data block from a mass storage device and transmitting the user defined data from the data block to the host processor within the frame.
Description:
The present invention relates to input/output (I/O) subsystems for automated data processing equipment, and in particular to I/O subsystems employing serial protocols. BACKGROUND OF THE INVENTION An Input/Output (I/O) channel subsystem is used to transfer information between I/O devices and the main storage of a host processor. An I/O channel, for example, may connect the host directly to a mass storage device (e.g., disk or tape drive). In the case of a mainframe host processor, the channel is usually coupled to one or more device controllers. Each device controller is in turn connected to a plurality of mass storage devices. The I/O channel subsystem typically has an independent I/O processor which asynchronously controls the movement of data between the external devices and system memory. This allows data processing by an execution unit to proceed simultaneously with I/O operations. By offloading the low-level I/O management tasks from the execution unit to the I/O processor, system throughput is enhanced. I/O channel subsystems use distinct physical media and I/O protocols that differ from the communications media and protocols used in communications networks. Throughout the 1980's, the typical I/O subsystem in large processing systems used a copper "bus and tag" medium and a parallel channel protocol. Parallel channels were limited in distance to about 130 meters between the host and an attached device. In recent years, the use of fiber optic I/O channels and serial I/O protocols has gained wide acceptance. These channels have advantages of higher data rate and longer allowable separation between the host and the attached devices. An exemplary serial I/O channel protocol is defined in the ESCON I/O Interface specification, Document No. SA22-7402-02, published by IBM Corporation, 1991, which is incorporated herein by reference for its teachings on I/O channel protocols. ESCON(TM) is a trademark of the IBM corporation. In the ESCON protocol, as in other protocols, information is transmitted by the channel organized into frames. The frames include control information (e.g., source address, destination address, pacing information for dynamically adjusting the flow of frames in both directions, link control information, etc.) and may contain user defined data. Link-Control frames are exchanged between a host and a device controller to establish and maintain a logical connection between them. Device level frames control I/O operations and are used to transfer data. All of the frames include a start-of-frame (SOF) delimiter, a header, a cyclical redundancy checksum (CRC) and an end-of-frame (EOF) delimiter. Data frames include user defined data after the header. An SOF may be a connect SOF (CSOF), which establishes a dynamic link, or a passive SOF (PSOF), which is sent if a dynamic link is already established. An EOF may be a passive EOF (PEOF), a disconnect EOF (DEOF) or an abort EOF (AEOF). A PEOF is sent if the dynamic link will remain connected after the EOF is sent. A DEOF causes disconnection of the dynamic link after processing the frame that ended with the DEOF. An AEOF, or abort delimiter, is sent if the sender detects an error condition and is unable to complete the transmission of a normal frame. The recipient of a frame ending with an AEOF discards the frame. The ESCON(TM) protocol specifies use of a defined set of 10 bit sequences forming normal "D" data characters and special "K" characters. The K and D characters are defined in U.S. Pat. No. 4,486,739 to Franaszek et al., which is hereby incorporated by reference therefore. The D characters are encoded from/decoded into eight bit combinations. The K characters only have meaning within "ordered sets". The ordered sets include K characters and combinations of K and D characters in predetermined sequences. These ordered sets provide for delineation of frames, control of I/O links (between host I/O subsystem and device I/O subsystem), and synchronization between sender and recipient. U.S. Pat. No. 5,133,078 to Minassian et al. describes a serial frame processing system for processing incoming data asynchronously from the circuits in which the data are later processed. An In Buffer Fill State Machine checks the frame, including the CRC characters for validity and stores the frame in an Input Buffer (IB). An In Frame State Machine (IFRSM) extracts portions of the frame from the IB for decoding and moves the remaining portion of the data into an output buffer. Minassian et al. describe checking incoming frames (checking the CRC and ensuring that the frame includes an SOF and an EOF) while the Device Information Block (DIB) is being received. Additional processing of incoming frames which is asynchronous from the operations of the microprocessor controlling the channel is desired. SUMMARY OF THE INVENTION The present invention is apparatus for use in an Input/Output (I/O) subsystem. The I/O subsystem is coupled to a serial data transfer medium that transmits data from a sender to a recipient that has a parallel storage medium. The I/O subsystem processes a frame comprising user defined data and frame control data. The frame is received over the serial data transfer medium. The apparatus includes a mechanism for receiving and validating the frame from the serial data transfer medium. The receiving mechanism transmits the user defined data to a first-in, first-out (FIFO) buffer. A mechanism is provided for forming a block header. The block header comprises control data that are used by the recipient of the user defined data. The block header forming mechanism is distinct from the FIFO buffer. A switching mechanism is coupled to receive the block header and a subset of the user defined data. The switching mechanism transmits either the block header or the subset of the user defined data to the parallel storage medium of the recipient. A control mechanism provides signals to configure the switching mechanism to alternately transmit the block header and the subset of the user defined data to the parallel storage medium. By alternating the block header and data, a data block is formed having a size that equals the native sector size of the recipient.
BRIEF DESCRIPTION OF THE FIGURES FIG. 1 is a block diagram of an exemplary system according to the present invention FIG. 2 is a block diagram of the channel transmit function shown in FIG. 1. FIG. 3 is a block diagram of the channel receive function shown in FIG. 1. FIG. 4 is a detailed block diagram of the transmit function shown in FIG. 2. FIG. 5 is a block diagram of the unpacker shown in FIG. 4. FIG. 6a is a block diagram of the transmit frame register logic shown in FIG. 4. FIG. 6b is a block diagram of a second exemplary transmits frame register logic function, FIG. 7 is a block diagram of the data path control logic shown in FIG. 4. FIG. 8 is a block diagram of the DMA logic shown in FIG. 1. FIG. 9 is a block diagram of the FIFO & control function shown in FIG. 4. FIG. 10 is a detailed block diagram of the receive logic shown in FIG. 3. FIG. 11 is a block diagram of the control logic for switching the received data processed by the receive logic shown in FIG. 10. FIG. 12 is a detailed block diagram of the receive frame buffer logic shown in FIG. 11. FIG. 13 is a block diagram of a packer circuit for deserializing the data stream output by the switch shown in FIG. 11. FIG. 14 is a block diagram showing a device controller including an I/O channel according to the invention, coupled to the host system shown in FIG. 1. FIG. 15 is a state diagram of the sequence receive logic shown in FIG. 10.
DETAILED DESCRIPTION OVERVIEW Referring first to FIG. 1, the present invention is an apparatus and method for transferring user defined data between a parallel storage medium 38 and a serial link driver 34. The apparatus is suitable for use in the I/O channel 20 of a processor system 23, such as a 2200 series system manufactured by the UNISYS corporation of Bluebell, Pa. If processor 23 is a mainframe computer, the parallel storage medium may be a data buffer 38 for receiving and storing a portion of the information stored in the main memory 25 of the processor 23. A bus interface 24 couples the parallel storage medium 38 to the bus of the mainframe. The bus interface is used to transfer data to data buffer 38 during an output operation, and to receive the data from data buffer 38 during a receive operation. The Small Computer Systems Interface (SCSI) channel interface of the UNISYS A Series processor system is an example of a bus interface that performs this function. Processor 23 may also include a microcomputer (not shown), in which case the parallel storage medium may be the main random access memory (RAM)
a separate bus interface 24 need not be used when implementing the invention in a microcomputer. The apparatus is also suitable for use in the I/O channel 20 of a device controller 37 (shown in FIG. 14). The device controller channel communicates with the I/O channel of a processor such as host 23. In the case of a device controller 37, the parallel storage medium may be a buffer identical to data buffer 38 (FIG. 1), which is used to store a portion of the data in a mass storage device 39 attached to the device controller 37. Referring again to FIG. 1, the serial link driver 34 transmits a frame of data over a serial data transfer medium 36, or receives a frame of data from the serial medium 36. The serial link driver 34 may be, for example, a conventional Am79168/Am79169 TAXichip(TM) Transmitter/Receiver chip set manufactured by Advanced Micro Devices. According to one aspect of the invention, a parallel storage medium 38 receives the user defined data from the processor 23 via a bus interface 24. The data buffer 38 has sufficient storage space to simultaneously store enough data to form several data frames. The same data buffer 38 may also be used to store user defined data received over the serial transfer medium 36, before forwarding the user defined data to the host processor 23. The exemplary serial data transfer medium 36 is an optical fiber, but the serial medium may also be coaxial cable. A fiber interface facility 26 converts the data into a serial stream and forms frames for transmission over the serial data transfer medium 36. The fiber interface facility 26, in conjunction With the microprocessor 52 implements the rules of the channel I/O protocol that is used. The fiber interface facility 26 includes a control data transmit facility 31, including items 72-76 (described below with reference to FIG. 2) for forming and transmitting control data. The types of control data used depend on the channel protocol that is selected. The exemplary embodiment of the invention implements the ESCON(TM) protocol as specified in the "ESCON I/O Interface" document, referenced above. The invention may also be applied to systems that employ other I/O protocols. The control data include link level control sequences, a start-of-frame (SOF) sequence, a frame header, a cyclical redundancy checksum (CRC) and an end-of-frame (EOF) sequence. The circuitry 72-76 that provides the control data is distinct from the parallel storage medium 38. The fiber interface facility 26 interleaves the transmission of control data and user defined data to form a complete data stream for transmission to the serial link driver 34. The control data are sent from host 23 to the recipient (not shown) of the frame, to allow the recipient to process the frame, and to perform handshaking functions to maintain the link between host 23 and the recipient. The fiber interface 26 also includes a control data receive facility 29, including items 82-86 (described below with reference to FIG. 3). The control data receive facility 82-86 processes ordered sequences, SOF delimiters, frame headers, CRC and EOF delimiters that are received in the incoming data stream from the serial link driver 34. Referring again to FIG. 1, a microprocessor 52 provides the high level control for the channel 20. The microprocessor receives channel commands from the host processor 23 and configures the fiber interface 26 to execute the channel data transfer functions. Microprocessor 52 may be, for example, an 80960CA processor manufactured by the Intel corporation. A programmable read only memory (PROM) 58 stores the instructions that are executed to boot the microprocessor. A static random access memory (SRAM) is provided for storing the microcode that configures the hardware in the fiber interface 26. Referring now to FIG. 2, the transmit function 31 of the fiber interface facility 26 is shown in greater detail. The control data transmit facility 72-76 is distinct from the data buffer 38. Individual elements 72-76 are described in greater detail with reference to FIGS. 4-9 below. A switching mechanism 80 (described in detail below with reference to FIG. 4) is coupled, to the data buffer 38 for receiving the user defined data, and to the control data facility 72-76 for receiving the control data. The control data facility includes sequence generation logic 72 for generating link level control sequences, SOF generation logic 73, a transmit frame buffer 74 for storing a frame header, CRC generation logic 75 and EOF generation logic 76. The switching mechanism 80 is also coupled to the serial link driver 34 for providing either the user defined data or one of the sources 72-76 of control data to the serial link driver 34 at any given time. A data path control mechanism 90 (shown in FIG. 4) configures the switching mechanism 80 to provide the sequences (e.g., idle sequence), SOF, frame header, user defined data, CRC and EOF in order, switching from the current source of data to the next source of data, when the current source of data has completed transmission. By selecting and transmitting each type of control data or user defined data at the appropriate time, the frame is formed. The switching occurs autonomously, without intervention from microprocessor 52. In the exemplary embodiment, each function 72-76 is implemented using a respectively different dedicated hardware component, and the switching function 80 is also implemented in hardware. This architecture reduces the number of microprocessor interrupts and frees up the microprocessor 52 (shown in FIG. 1) to perform high level supervisory functions and to process exceptional conditions and errors. The functions 72-76 all operate asynchronously from the host processor 23, the parallel storage medium 24 and the data buffer 38. Each of the transmit control data functions 72-76 is tailored to perform an individual function with high speed and efficiency. The same apparatus is used to form and transmit link control and status frames and device control and status frames, which do not include any user defined data. The format of these frames is defined in the I/O protocol definition, which is the ESCON(TM) I/O Interface for the exemplary embodiments. All of the same circuits are used to transmit frames that do not contain data, except that the switching facility 80 does not receive any user defined data from the data buffer 38 when transmitting a control frame. Data are only transmitted from the control data facility components 72-76. FIG. 3 is a block diagram of an exemplary receive function according to the invention. The receive function is architecturally similar to the transmit function, in that respectively different elements 82-86 are provided for processing incoming control data. Items 82-86 are described in greater detail below with reference to FIGS. 10-13. Sequence recognition logic 82 processes link level ordered sequences (e.g., idles) to identify a change of the state of channel 20. An SOF recognition function 83 detects the receipt of an SOF delimiter. A receive frame buffer 84 stores an incoming frame header, so that the header may be verified. A CRC check function 85 verifies the user data within the frame. The EOF recognition function 86 identifies an EOF delimiter which indicates the end of the frame. Receive switching facility 81 is analogous to the transmit switching facility 80. Switching facility 81 includes logic to determine when to switch the incoming data stream from one of the processing functions 82-86 to another, so that each portion of the data stream is processed correctly. According to the invention, an expected type of frame is determined, and the data in the frame buffer 84 are compared to the expected type information, to determine whether the type of frame received is an "expected type" of frame, e.g., complying with the link and device level I/O protocols. By providing hardware elements to generate control data and perform the switching between the user defined data and the control data, microprocessor interrupts are reduced and the microprocessor resource is freed up to direct the high level functions and respond to error conditions. Similarly, by using separate hardware elements to process received control data and to direct the switching of the control data to the hardware, efficient use is made of the microprocessor 52. According to another aspect of the invention, shown in FIG. 9, distinct elements 354 and 356 are provided for asynchronously forming device block header data and error detection code (EDC) data, respectively. Control elements 352, 362 and 366 inject these data into the received data stream en route to the data buffer 38 (shown in FIG. 3). In the transmit path 31, the control elements 352, 362 and 366 strip the header and EDC out of the data stream before transmission over the serial medium 36. Element 354 checks the block header and element 356 checks EDC data. THE EXEMPLARY EMBODIMENTS FIBER INTERFACE TRANSMIT FUNCTIONS FIG. 4 is a block diagram of the transmit logic partition 31 of the fiber interface circuitry 26. The transmit logic 31 includes the transmit data path control 90 (described below with reference to FIG. 7), switching circuitry 80, the Cycle Burst Control circuitry 94, CRC generation and parity check circuitry 75, character generators 77 (including sequence generation 72, SOF generation logic 73 and EOF generation logic as shown in FIGS. 2 and 7), and the output synchronizer 96. Each of these functions is explained in greater detail below. The switching facility 80 receives the control data and user defined data from the sources 38 and 72-76 shown in FIG. 2. As shown in FIG. 4, switching facility 80 includes a plurality of multiplexers 102, 106 and 110. Multiplexer 110 selects either ordinary character (frame) data 109a, or special character data 109b. Transmission frames include ordinary character data 109a, which comprises a header, a devise information block or DIB (for device frames) and a cyclical redundancy checksum (CRC). The special character data 109b include ordered sequences that are transmitted while establishing the link, and idle characters that occur to maintain synchronization in between frames after the link is established. The special character data 109b also include the start-of-frame (SOF) delimiter and the end-of-frame (EOF) delimiter. Data path control 90 controls multiplexer 110 to select the special character path 109b from the character generator function 77 to transmit idle characters until an SOF is sent. Then data path control 90 signals multiplexer 110 to select path 109a. Multiplexer 102 has respective input terminals for receiving user defined data, via line 101a, from the First-in, First-Out (FIFO) & Control function 92, or for receiving header data, via line 101b from the transmit frame register 74. After the SOF has been selected for transmission, data path control 90 controls multiplexer 102 to select line 101b to transmit the header from the transmit frame register 74 (The transmit frame register 74 is described below with reference to FIG. 6A). When header transmission is completed, data path control 90 signals multiplexer 102 to select line 101a, to transmit the user defined data from the FIFO & Control function 92. The FIFO & Control function 92 receives the user defined data from the data buffer 38 via the unpacker 150 (described below with reference to FIG. 5). The FIFO & Control function 92 provides an intermediate storage medium (FIFO buffer 350, shown in FIG. 9) into which the user defined data are stored before transmission. In some cases (discussed below with reference to FIG. 9) the data buffer 38 and unpacker 150 may contain additional data besides the user defined data, the additional data including (but not limited to) error detection code (EDC) data. The EDC data are removed from the data stream by the FIFO & control 92, and only the user defined data are stored in the FIFO buffer 350, so that a continuous stream of user defined data is available in the FIFO & control 92 for transmission over the serial data transfer medium 36. The structure and purpose of the FIFO & control 92 is described in detail below with reference to FIG. 9. Referring again to FIG. 4, while the header and user defined data are being transmitted, they are also provided to the CRC generation function 75, which computes the CRC over the header and the user defined data, using a byte wise CRC generation technique. In the exemplary embodiment, the CRC is computed using the polynomial specified in the ESCON I/O Specification at pages 2-9 and 2-10. One skilled in the art could readily construct a CRC generator using that polynomial. The header and user defined data are passed through a delay function 104. The delay allows CRC function 75 to compute the CRC for transmission immediately after the last bit of user defined data. The delayed header and user defined data are provided to multiplexer 106 via line 105a. While the header and user defined data are being transmitted, data path control 90 controls the multiplexer 106 to transmit the byte stream it receives via line 105a. After the last bit of user defined data is transmitted, data path control 90 signals the multiplexer 106 to select line 105b for transmission. The CRC data are provided to multiplexer 106 via line 105b. The output byte stream from multiplexer 106 passes through a delay element 108. The delayed byte stream is then provided to line 109a. After the last bit of the CRC is transmitted, data path control 90 signals multiplexer 110 to select line 109b. Character generator 77 provides an EOF delimiter and then resumes sending idle characters over line 109b. In addition to the circuits shown in FIG. 4, the exemplary switching facility also includes circuitry (not shown in FIG. 4) for selecting one of the plurality of special characters provided by the character generator 77. This circuitry is described below with reference to FIG. 7. In FIG. 4, the Cycle Burst Control logic 94 includes a plurality of registers 95a-95g, the contents of which are provided to data path control 90. The Cycle Burst Control also includes logic that determines whether to start another frame. This logic compares the values in the amount register 95a and the (LIMIT-MAR) register 95f. The amount register 95a is loaded, under control of microcode (executed in microprocessor 52), with a value that represents the amount of data that must be present in the data buffer 38 at the start of frame transmission to guarantee an uninterrupted frame. If data buffer 38 is coupled to a host processor 23, the value stored in the amount register 95a is the size of the device information block (DIB). Alternatively, if the data buffer 38 is installed in a device controller 37 (FIG. 14), the value stored in the amount register 95a may also include control data, such as a device header and error detection code (EDC) that are stripped from a data block upon receipt from the mass storage device 39 (FIG. 14). Header/EDC stripping are described in greater detail below with reference to FIG. 9. Referring again to FIG. 4, the LIMIT-MAR (Memory Address Register) register 95f is loaded with a LIMIT-MAR value computed from the LIMIT and MAR in the DMA address control circuitry (shown in FIG. 8). When the data buffer 38 is read, the LIMIT value represents last byte requested and written in buffer 38, and the MAR value represents the address last read. Thus (LIMIT-MAR) is the amount of data remaining in the data buffer 38 for transmission within the frame. If the value in the LIMIT-MAR register 95f is greater than or equal to the value in the amount register 95a, the condition for automatically sending another frame is met. Burst Enable register 95b is set to place the hardware in a state which allows a frame to be sent if the conditions for automatically sending the frame are met. If Burst Enable 95b is set and DIB override register 95g is not set, then a frame will be sent if the amount register is less than or equal to the value of LIMIT-MAR (Memory Address Register). LIMIT-MAR represents the amount of data available in data buffer 38 for transmission, and is described below with reference to FIG. 8. Cycled Burst Mode register 95c is set to operate the data path control 90 in Cycled Burst Mode. In Cycled Burst Mode, the data path control 90 and switching facility 80 automatically alternate the transmission of control data and user defined data to form frames for transmission (This alternating is asynchronous with the activities of microprocessor 52). The DIB size register 95d is loaded by microcode (executed in microprocessor 52) with a standard DIB size value identifying the amount of user defined data to be included in each frame while operating in Cycled Burst Mode. The value in the DIB size register 95d is automatically loaded into the Frame Size decrementer 240a (shown in FIG. 7) within the data path control 90, while the system is operating in Cycled Burst Mode. The frame size value register 95e specifies how much of the frame is sent from the frame register 74. When in Cycled Burst Mode the frame register 74 contains only the frame header and the frame size value register 95e is set to the size of the header. If the DIB size override flag in register 95g is set, the transmission of a frame is forced, whether or not the automatic send condition is met (i.e., regardless of whether the amount of data available in the data buffer 38 is as great as the value stored in the LIMIT-MAR register 95f. The data sync function 96 provides the input signals to the TAXichip set 34 for transmitting the serial data stream over the fiber 36. Data sync 96 includes a 20 Megahertz crystal oscillator clock signal (CLK) for the TAXichip set 34. The STROBE signal is timed so that the positive going edge of the STROBE signal indicates that the data and command (CMD) signals are to be latched by the TAXichip. The command/data select (C/D) signal conditions the TAXichip to encode and transmit either the data stream transmitted by multiplexer 110 or a command stream (not shown). The command input signal is used to transmit the special characters ("K" characters). The output enable (OE) line signals to the TAXichip 34 to enable either or both of a pair of differential output lines or a single ended output line. One skilled in the art of designing digital signal communication circuitry could readily construct the data sync function to perform frequency matching. UNPACKER (SERIALIZER) FIG. 5 is a block diagram of the unpacker logic partition 150 including the unpacking registers 152 and 154 and unpacker control circuitry 158. Data are read from the data buffer 38 (FIG. 1) and stored in the unpacker 150. The data are transmitted from the unpacker 150 to the FIFO & control 92 (shown in FIG. 9). The unpacker logic 150 converts the four-byte parallel stream from data buffer 38 into a one byte stream. Referring to FIG. 5, the unpacking registers 152 and 154 are two 36 bit registers, controlled by the unpacker control circuitry 158. The first register 152 is loaded with four bytes of data from the data buffer 38 under control of the unpacker control 158. The Unpacker control circuitry 158 transmits a memory request (MR) to the arbitrate logic 302 (shown in FIG. 8). In the exemplary embodiment, the same data buffer 38 is used both for transmit and receive functions, and the arbitrate logic 302 allocates data buffer 38 accesses between the host bus and either one of the transmit 31 or receive 29 functions. The first register 152 is loaded when the unpacker control circuitry 158 receives a grant signal from the arbitrate logic 302. This signal is received in response to the memory request signal sent by unpacker logic 158. The other conditions for loading register 152 are that the device read direction is set and burst is enabled in the Burst Enable register 95b of the Cycle Burst Control circuitry 94 (shown in FIG. 4). The second register 154 is the unpacking register, which loads the data from the first register 152, on the clock following the loading of register 152 (if the unpacking register 154 is empty). The unpacker control circuitry 158 includes a 2 bit counter (not shown) to provide a multiplexer select signal 160 to a multiplexer 156. Multiplexer 156 receives the data output by the unpacking register 154. Multiplexer 156 rotates through, transmitting the signal 160 to select each of the four bytes 154a-154b in the unpacking register 154 successively. Each byte of data is then sent from multiplexer 156 to the FIFO & Control 92 (shown in FIG. 9). A prefill operation is performed for this pipeline to load the first four bytes of data into the unpacking register 154. This prefill operation occurs while the header is being sent from the transmit frame register 74 (FIG. 6A). Referring again to FIG. 5, when the unpacking register 154 is loaded with four bytes of data, the unpacker control circuitry 158 transmits a "data available" signal to the data path control circuitry 90 (FIG. 4). Even though the user defined data are not the first data in the frame--the SOF is first--data path control circuitry 90 (FIG. 4) does not begin transmitting the SOF until the first four bytes of data have been loaded into the unpacking register 154. This ensures that user defined data are available once the frame transmission is begun by transmitting the SOF. Consequently, there is no interruption in the transmission of data until after the EOF is sent. Referring again to FIG. 5, when the data path control 90 (shown in FIG. 7) receives the data available signal, it configures the switching facility 80 to begin the transmission of a frame. After the four bytes in the unpacking register 154 are transmitted, data path control 90 transmits a "byte request" signal to the unpacker control 158. This signal indicates to the unpacking logic that the unpacking register 154 is ready to receive the next four bytes, which are then loaded on the next clock cycle into register 154 from register 152. Then another four bytes of data are transferred from the data buffer 38 (FIG. 1) to register 152. If an error occurs, such that the unpacker is unable to deliver a steady stream of bytes, then unpacker control 158 transmits an "error" signal to data path control 90. Depending on the timing of the error, data path control may take different actions. If, for example, the SOF, header and user defined data are already being transmitted, data path control 90 may configure the character generator 77 to transmit an end of frame--abort (AEOF) sequence. It is understood by one skilled in the art that the packer may be implemented with registers 152 and 154 having different capacities if the byte stream coming from the data buffer 38 is more or less than 36 bits wide. TRANSMIT FRAME REGISTER FIG. 6A shows exemplary transmit frame register logic 184. This logic includes the frame register 74, a send-ready counter 182 and a read pointer 180. The transmit frame logic 184 performs three main operations:
(1) it receives frame header data from microprocessor 52, stores the header data in a transmit frame register 74, and transmits frame headers for both data frame
(2) it modifies the data stored in the frame register 74 to provide control information to the re and
(3) it provides a source of header data that is independent and distinct from the source (data buffer 38) of user defined data, so that a control frame may be transmitted by the channel 20 (FIG. 1), even when the channel 20 is unable to provide user defined data to form a data frame. The frame register 74 is a 16 byte register which holds header information or an entire small control frame (i.e., a frame that does not include any user defined data). If the entire frame is contained in the Frame register then the DIB size value register 95d in the Cycle Burst Control 94 (shown in FIG. 4) contains a value of zero, and the DIB Override flag 95g (shown in FIG. 4) is set to force the transmission of the control frame without checking whether there are sufficient user defined data (none is needed) in the data buffer 38 (FIG. 1). When in Cycled Burst Mode, the frame register 74 contains only the frame header, and the frame size value register 95e (shown in FIG. 4) is set to the size of the header. The frame register read pointer 180 points to the next byte to be sent from the frame register, it is loaded by microprocessor 52 and cleared by the Cycle Burst Control 94 when the Cycle Burst Control determines that it is time to send an EOF (so the transmit frame register 74 may be used to send the next frame) when in Cycled Burst Mode. In Cycled Burst Mode, the frame starts in byte 0 of the frame register 74. When the read pointer 180 reaches the value stored in the frame size value register 95e (shown in FIG. 4), the data path control 90 switches multiplexer 102 to select the data stream from the unpacker 150 (shown in FIG. 5) until a number of bytes specified in the frame size decrementer counter 240a (shown in FIG. 7) have been transmitted. Data path control 90 also transmits a signal 192 to the read pointer 180 to clear the read pointer, so that the register contents may be read again when transmitting the next frame. The first function of the transmit frame logic 184 has already been described in detail. The second function of logic 184 (modifying the control data) enables logic 184 to send "readies" (frames in which the ready bit 74a is set). As defined in chapter 6 of the ESCON I/O Interface specification referenced above, the header of every device frame (i.e., frame associated with the execution of an I/O operation) includes several bits of information that are defined by the source and destination, and by the nature of the information exchange. This information is generally the same for every frame sent during a single I/O operation. Generally, once the microprocessor 52 loads the header data into the transmit frame register 74, the same header data are sent from the register 74 for each frame within the same I/O operation. One bit in the header, the ready bit 74a, is used for pacing and changes dynamically between frames, even within the same I/O operation. The ready bit 74a, when set to one, indicates that the channel 20 (FIG. 1) which is sending data is ready to accept a new data request from the recipient (not shown) of the data. For example, the channel 20 may be transmitting the first 10 kilobytes of data (in an I/O operation that includes 50 kilobytes) in response to an I/O request from the recipient for the first 10 kilobytes. The recipient of the data only requests as much data as it can accept, which depends on the availability of buffer space within the recipient. When the recipient is ready to accept more data, it sends another request to the sender, channel 20. When channel 20 has processed the request (described in detail with reference to the receive functions of channel 20 in FIGS. 10-12), it sets the value of the ready bit 74a to "one" in the header of the next frame that is transmitted. Thus the sender of data sends "readies" to the recipient for pacing the data requests. The method for setting the ready bit 74a is now described. When a request has been processed, and the information therefrom is transmitted to the microprocessor 52 (FIG. 1), the channel 20 is ready to receive another request. The send ready counter 182 tracks the transmission of readies. The Send Ready counter 182 is a 4 bit counter which is incremented and cleared by microprocessor 52 and decremented by hardware (i.e., by a signal from data path control circuitry 90 which indicates that the frame has been sent). Microprocessor 52 sends an increment pulse signal 186 to the send ready counter 182 to increment the value held by the send ready counter 182. The send ready counter 182 provides an output signal 188 to the transmit frame register 74. The value of signal 188 is set to "one" if the count in send ready counter 182 is greater than zero, and is reset to "zero" if the count is equal to zero. When the signal 188 is set to "one", the ready bit 74a stored in the transmit frame register 74 is set to "one." The header in the next frame transmitted has its ready bit set to "one." After the next frame is sent the data path control 90 provides a "sent frame" signal 190 to decrement the value held by the send ready counter 182. When enough "readies" have been sent to decrement the ready counter 182 to "zero", the value of the output signal 188 of counter 182 is reset to "zero." Subsequent frame headers will have their ready bits set to "zero" until the microprocessor 52 sends another increment pulse 186 to the send ready counter 182. Thus, the transmit frame logic 184 relieves the microprocessor of the task of tracking how many readies are to be sent, and in which frames the ready bit is set. The microprocessor 52 need only identify, via the increment pulse 186, that a request has been processed and a ready can be sent by the transmit frame logic 184. The ready is sent asynchronously from the increment pulse 186. If a frame is being transmitted when the microprocessor 52 completes the processing of a request, the microprocessor need not wait until the current frame has completed transmission before sending an increment pulse 186 to the send ready counter 182. The increment pulse 186 may even be sent while a header is being transmitted from the transmit frame register 74. Whenever the next header is transmitted from transmit frame register 74, the ready is sent, with no intervention by the microprocessor 52. Although the exemplary embodiments use the transmit frame logic to modify the ready bit used in the ESCON(TM) protocol, it will be understood by one skilled in the art that this method and structure may be applied in other I/O protocols to change a variety of control data asynchronous with any processing performed by the microprocessor 52. A frame register 74 and send ready counter 182 may be used to turn on a bit asynchronously to the generation of frames, with assurance that the set bit is transmitted in one and only one frame. The bit may be applied by the recipient as an instruction to initiate another process that is asynchronous to the I/O operation. The described circuitry also allows the system to turn on the bit for a dynamically selected number of frames as the microprocessor issues multiple increment pulses 186 before the counter 182 is decremented to zero. Referring now to FIG. 6b, another variation of the transmit frame logic 185 is shown. Elements that are the same as in logic 184 of FIG. 6a have the same reference numerals. Two transmit frame registers 194a and 194b are included in logic 185. Each of these registers is coupled to a respective input port of a multiplexer 196. The output signal from the send ready counter 182 is provided to the input select terminal of the multiplexer 196, instead of to the transmit frame register. The output signal from the multiplexer 196 is transmitted to multiplexer 102 (shown in FIG. 4) as the frame header. In the embodiment of FIG. 6b, When the output signal 188 of the send ready counter 182 has a value of "zero" the header signal output from the multiplexer 196 is taken from the first transmit frame register 194a to provide a first header. But if the send ready counter 182 is incremented and the output signal 188 has a value of "one", then an alternate header is taken from register 194b. It is understood by one skilled in the art that this method may be used to substitute an entirely different header, or to change any subset of the frame header data stored in the transmit frame register 194a for use in a single frame. A bit 74b is varied based on the state of the Cycle Burst Control logic 94. Cycle Burst Control logic 94 (shown in FIG. 4) monitors the LIMIT-MAR amount in register 95f (also shown in FIG. 4). When all of the user defined data in a data transfer have been loaded into the data buffer 38, a bit 199 is set in Cycle Burst Control 94 by microprocessor 52. Once bit 199 is set, when the value of the LIMIT-MAR register 95f becomes less than or equal to the value in the DIB size register 95d, the last frame is being transmitted using a register (a "last frame" register, not shown) to determine its length. Cycle Burst Control 94 changes the select signal sent to multiplexer 198, changing an END bit 74b in the transmit frame register 74. This bit tells the recipient that this is the last frame of a data transfer. The third function of the transmit frame logic 184 described above (an independent and distinct source of frame header data), provides the ability to maintain a full-duplex exchange of control information between the channel 20 and a device or controller coupled to the channel via the serial data transfer medium 36. This full-duplex control data exchange may be maintained, even if only half-duplex exchange is possible for user defined data. For example, in the ESCON(TM) I/O Interface protocol which is followed in the exemplary embodiment, full-duplex control and half-duplex data exchange are specified. Because the protocol only requires half-duplex data I/O, a single buffer 38 (FIG. 1) is used in the exemplary embodiment for both the transmit and receive functions of the channel 20. Using a single data buffer 38, it would not be possible to extract frame header data from the buffer 38 at the same time that the receive path of the channel 20 is transmitting received data to the host 23 (FIG. 1). Nor would it be possible to extract the frame header data while the host interface 24 or the microprocessor 52 (both shown in FIG. 1) has access to the data buffer 38. This problem is mitigated in the subject invention by using a distinct frame register 74 to form a control frame using the transmit frame register, the CRC generator 75 and the character generator 77 (all shown in FIG. 4). This may be done without gaining access to the data buffer 38. TRANSMIT DATA PATH CONTROL FIG. 7 is a block diagram of the data path control function 90. Data path control 90 (DPC) includes a plurality of registers and counters for controlling the selection of one of several sources of user defined data or control data for transmission over the serial transfer link 36. As described above with reference to FIG. 4, the character generator 77 comprises a sequence generator 72, an SOF generator 73 and an EOF generator 76. FIG. 7 shows an exemplary embodiment of the character generator 77 in which the special character bit sequences (i.e., those designated K28.n, where n=1, 2 or 4-7) are hardwired into the DPC logic 90. In the exemplary embodiment, each character is stored in a respectively different register. The standard bit patterns that form the idle character and the SOF and EOF delimiters are set forth in Appendix B of the ESCON(TM) I/O Interface specification, referenced above. Only the second character 208 of the sequence functions 72 (which may be a data character) may take on multiple values in the exemplary embodiment. It is understood by one skilled in the art that a distinct valid data character generator may also be provided for each of the valid data characters used, similar to the technique used in the special characters. Character selection logic 242 provides a signal 243 to the input select terminal of multiplexer 202. If the value of signal 243 is zero, then a sequence function from multiplexer 204 is transmitted from the output terminal of multiplexer 202. If the value of signal 243 is one, then an SOF delimiter is transmitted from multiplexer 210. If the value of signal 243 is two, then an EOF delimiter is transmitted from multiplexer 220. In between bursts (frames) the sequence function register is selected. The idle character is defined as the K28.5 character, transmitted a minimum number of times. The minimum idle register 240c specifies the minimum number of pairs of idle characters to be sent while in Cycled Burst Mode. The minimum idle register 240c is loaded by microprocessor 52 (FIG. 1). The idle character is provided by block 206, when multiplexer 202 is set to select the input from multiplexer 204, and multiplexer 204 repeatedly selects the K28.5 character from block 206. A frame starts when the SOF characters are selected. SOF ordered sets comprise two special characters. The SOF ordered set is formed if the character selection logic 242 signals multiplexer 202 to select the data received from multiplexer 210. Multiplexer 210 transmits a first character from the output terminal of multiplexer 212, followed by a K28.7 character from block 216. The first character selected by multiplexer 212 may either be a K28.1 for a CSOF (connect SOF), or a K28.5 for an PSOF (Passive SOF). The microprocessor 52 (shown in FIG. 1) loads a PSOF register (not shown). The value in the PSOF register is loaded via input signal 211 to the input select terminal of multiplexer 212 to select a CSOF or PSOF, as appropriate. After the SOF characters, DPC 90 transmits a signal 252 to the input select terminal of multiplexer 102 (shown in FIG. 4) to select the control data from the transmit frame register 74. The amount of data transmitted from frame register 74 is the number of bytes specified in the frame register size value (e.g., 16 bytes in the exemplary embodiment). When the frame register 74 has transmitted the entire header, the character selection logic 242 of DPC 90 transmits signal 254 to the input select terminal of multiplexer 106 (shown in FIG. 4) to select the user defined data from the FIFO & Control 92. The number of bytes of user defined data to be transmitted in the frame is loaded into the frame size decrementer 240a. In the exemplary embodiment, in Cycled Burst Mode, the DIB size in register 95d of the Cycle Burst Control circuitry (shown in FIG. 4) is loaded into the frame size decrementer 240a as the initial value. The frame size decrementer 240a counts down from its initial value to zero to identify when to start sending the EOF delimiter. If the frame is not a data frame, the en